The invention relates to microcomputers.
Single chip microcomputers are known including external communication ports so that the chip may be connected in a network, including for example connection to a host microcomputer for use in debugging routines. Such systems are also known in which each of the interconnected microcomputer chips has its own local memory. For speed of communication on on-chips it is common for bit packets to be transmitted between modules on a chip in a bit parallel format. However problems arise in both power consumption and available pin space in providing for external off-chip communications in the same parallel bit format as that used on-chip. Such microcomputers require access to instruction or code sequences and for efficient operation it is desirable for the instructions to be retrievable from locations within the address space of the CPU. One approach described in co-pending European patent application number 97308517.8 is to provide an on-chip external communication port forming part of the memory address space of the CPU from which instructions may be fetched and which translates between a parallel format on-chip and a less parallel format for off-chip communications. By itself, however, this approach does not address the following problem. When an external computer is linked to the external communication port, the performance of the system may be poor if a single communication protocol runs all the way from the chip to the external computer. This is because the on-chip protocol is typically a low-level protocol of a lower latency than the protocols that are most suitable for use at the external computer. Also, the on-chip protocol can be electrically fragile, and unreliable if run over greater lengths than around 1.5 m. This imposes a physical limitation on the debugger if the on-chip protocol is used all the way from the chip to the external computer.
According to a first aspect of the present invention there is provided a computer system comprising a microprocessor on a single integrated circuit chip connected to an external computer device via an adapter device; the integrated circuit chip having an on-chip CPU with a plurality of registers and a communication bus providing a parallel communication path between the CPU and a first memory local to the CPU, the integrated circuit further comprising an external communication port connected to the said bus on the integrated circuit chip, the port having an internal connection to the said bus of an internal parallel signal format and an external connection to the adapter unit of a first external format less parallel than the said internal format; the adapter device being connected to the external communication port with the first external format and to the external computer with a second external format having a higher latency than the first external format, the adapter device having an interface for translating between the first external format and the second external format; the external computer device having a second memory local to the external computer device; and the second memory being accessible by the CPU through the port, the port forming part of the memory address space of the CPU from which instructions may be fetched, whereby the port may be addressed by execution of an instruction by the CPU.
Preferably said on-chip CPU includes pointer circuitry for identifying the location of a next instruction for execution by the CPU and said pointer circuitry is operable to point to an address in said second memory.
According to a second aspect of the present invention there is provided a method of operating a computer system comprising a microprocessor on a single integrated circuit chip connected to an external computer device via an adapter device; the integrated circuit chip having an on-chip CPU with a plurality of registers and a communication bus providing a parallel communication path between the CPU and a first memory local to the CPU, the integrated circuit further comprising an external communication port connected to the said bus on the integrated circuit chip, the port having an internal connection to the said bus of an internal parallel signal format and an external connection to the adapter unit of a first external format less parallel than the said internal format; the adapter device being connected to the external communication port and the external computer with a second external format having a higher latency than the first external format; the external computer device having a second memory local to the external computer device; and the method comprising transmitting bit packets on the said bus with an internal parallel signal format, translating the packets in the external port to an external format less parallel than the internal format, addressing the second memory by the CPU through the port, the port forming part of the memory address space of the CPU from which instructions may be fetched, by execution of an instruction by the CPU, and translating in the adapter unit between the first external format and the second external format and thereby fetching an instruction from the second memory through the port.
Preferably bit packets are generated with a destination identifier within each packet, said external communication port translating bit packets between said internal and external formats while retaining identification of said destination. Preferably bit packets are generated with a source identifier within each packet, said external communication port translating bit packets between said internal and external formats while retaining identification of said source.
Preferably the routing unit routes to the external computer device a request by an on-chip module to access a memory address which is not mapped to the second or third memories. The on-chip module could be, for instance, a CPU or an interface device.
Preferably said translation of bit packets is between an on-chip bit parallel format and an external bit serial format.
In one arrangement said first memory has software executed by said on-chip CPU and said second memory has software executed by said on-chip CPU in a debugging routine for said on-chip CPU.
Alternatively or additionally said second memory has software executed by said external computer device in a debugging routine for said on-chip CPU.
Preferably said on-chip CPU includes pointer circuitry for identifying the location of a next instruction for execution by the CPU and said pointer circuitry is loaded with a pointer value pointing to an address in said second memory.